Fixed and Floating point-Based High-Speed Chaotic Oscillator Design with Different Numerical Algorithms on FPGA

Abstract

In this paper, the design of 3D PC chaotic system has been implemented using Euler, Heun, RK4 and RK5-Butcher numerical algorithms in VHDL with 32 bit IQ-Math fixed point number format (16I-16Q) on FPGA. The chaotic system designed with different numerical algorithms has been tested by being synthesized in Xilinx Virtex–6 (xc6vlx75t) FPGA chip. Additionally, the statistics of FPGA chip resource consumption have been investigated. It has been observed that the chaotic oscillators that designed on FPGA in fixed point number format have not only higher operating frequencies but also lower resource consumption ratio with respect to observed results and floating point designs in literature. As a result, various chaos based engineering applications can be performed using chaotic system model that realized in fixed point number format with different algorithms as hardware.