IQ-Math Based Designing of Fourth Order Runge-Kutta Algorithm on FPGA and Performance Analysis According to ANN Approximation

Abstract

In this paper, the design of the fourth order Runge-Kutta (RK4) algorithm has been performed using 32- bit IQ-Math (16I-16Q) fixed point number format in VHDL on FPGA. The designed system has been implemented into 3-B Jerk chaotic system. The design has been synthesized in Xilinx ISE Design Tools 14.7 programmer and it has been implemented in Xilinx Virtex–6 FPGA chip.The performance analyses have been carried out by evaluating the maximum operating frequencies and chip statistics that obtained from Place&Route process of FPGA-based designs. The comparative analyses between RK4 numeric-based Jerk chaotic system designed in fixed point number format on FPGA and ANN-based Jerk chaotic system on FPGA existing in literature have been performed. Accordingly, it has been observed that the numeric-based Jerk chaotic oscillator has not only greater operating frequency but also lower chip resource ratio. In future, chaos based various engineering applications can be carried out utilizing the Jerk chaotic system model implemented in FPGA-based fixed point number format.